Date
Place
- Room C (Room 323)
- YLC. Young Leaders Conference
- August 20, 2015 (Thursday)
- 11:00 ~ 12:30
- [YLC-6]
- 11:50 ~ 12:00
- Title:An Optimal ASG Driver Circuit with New Multi-Level Clock Driving Technique
- Sheng-Chin Hung, Yi-Hsuan Hung, Chien-Hsueh Chiang, and Yiming Li (Nat'l Chiao Tung Univ., Taiwan)
Abstract: For the display panel, the correct pixel data voltage is the most important factor of amorphous silicon gate (ASG) driver circuit which depends on short falling time and minimal ripple to reduce the misoperation of pixel data voltage. In this work, a new ASG driver circuit's dynamic characteristic is optimized, where the explored circuit is consisting of 14 hydrogenated amorphous silicon TFTs.
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