Date

Place

Room C (Room 323)
YLC. Young Leaders Conference
August 20, 2015 (Thursday)
11:00 ~ 12:30

[YLC-4]
11:30 ~ 11:40
Title:Effect of Interface Location within Solution-Processed In-Ga-Zn-O Thin-Film Transistors
Jae Won Na, Yeong-gyu Kim, and Hyun Jae Kim (Yonsei Univ., Korea)
Abstract: Among many amorphous oxide semiconductors (AOSs), In-Ga-Zn-O (IGZO) is emerging as a promising candidate to replace amorphous Si in TFTs. Although most IGZO TFTs are fabricated using the conventional vacuum techniques, many research groups are focusing on solution-processed IGZO TFTs due to their advantages such as low cost and simplicity in material composition. However, the solution-processed IGZO TFTs have inferior electrical characteristics, compared with the conventaional vacuum-processed IGZO TFTs. The cause for such inferiority is believed to be pin-holes and pore sites created during solvent volatilization. In order to overcome the degradation of electrical characteristics caused by pin-holes and pore sites, we previously introduced multi stacked IGZO TFT structure. However, the multi stacked IGZO TFT structure inevitable creates interfaces within the active layer, and effects of the interfaces are not thoroughly studied yet. Thus, we have fabricated three types of double stacked IGZO TFTs with interfaces at different locations within the active layer. The electrical characteristics of the three types of double stacked IGZO TFTs showed an increasing tendency, as the interface moved further from the gate insulator: mobility improved from 0.35 to 1.7 cm2/Vs, on current increased from 2.41 x 10-5 to 9.22 x 10-5 A. ?
PDF Download

Type