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Program

Date
Place
  • Room H (Room Hall 1, 1F)
  • P2. Poster Session II
  • August 21, 2015 (Friday)
  • 14:00 ~ 15:30
  • [P2-6]
  • 14:00 ~ 15:30
  • Title:The Fabrication and Characterization for Top Gated Sol-Gel InZnO Transistors
  • Tsung-Yen Lin (Nat'l ChangHua Univ. of Education, Taiwan), Chun-Cheng Cheng (AU Optronics Corp., Taiwan), Chi-Yen Huang, and Yu-Wu Wang (Nat'l ChangHua Univ. of Education, Taiwan)

  • Abstract: This study focuses on the fabrication and characterization for the top gated sol-gel InZnO (IZO) transistors. Oxide transistors have attracted much attention due to their superior device properties, especially low leakage current and high field effect mobility, than traditional amorphous silicon transistors in recent years. Sol-gel method for fabricating oxide semiconductor, as a low cost and large area compatible technique, has been reported many times?1-4. However oxide Semiconductors were known as humidity and oxygen sensitive materials, an appropriate passivation layer is needed for preventing the damage from outside atmosphere. Hence in this article, several polymer materials, such as PI, PVP and PMMA were investigated to serve as the top gate insulator for sol-gel IZO transistors, in addition, providing passivation for this IZO layer.?The PVP sample has the highest mobility ~0.108 cm2/vs, but the largest leakage current ~2 nA. The hybrid PVP/PMMA sample has the highest on/off current ratio ~ 104.

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