Date

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[P2-38]
14:00 ~ 15:30
Title:Top Gate Structured Inverters with Solution Processed IGZO and PMMA
Ji-Hwan Kim, Jin-Ho Kim, Dong-Hoon Lee, Eung-Kyu Park, Sihan Wang, Hyeong-Jun Cho, and Yong-Sang Kim (Sungkyunkwan Univ., Korea)
Abstract: In this study, we designed inverter with top gate structured thin film transistors. The TFTs were fabricated by spin coating a-IGZO and PMMA on SiO2, which reduces the process steps and fabrication cost. The PMMA layer has a dual role in top gate structure. It works as a gate insulator and also as a channel passivation layer. The channel passivation layer suppresses the electric-field-induced threshold voltage instability, which is caused by the adsorption of oxygen and moisture molecules from the atmosphere. The channel width/length ratios (W/L) of load and drive TFTs were 600/100 ��m and 6000/100 ��m, respectively. The enhancement mode inverter showed a gain of 2.08, output high voltage (VOH)= 25 V, output low voltage (VOL)= 4.2V, input high voltage (VIH)= 0V, input low voltage (VIL)= 10 V, and Vth= 5V at VDD= 30 V and sweep VIn= -30 to 30 V. The VOH of inverter is low because of the voltage drop by load TFT��s threshold voltage and trapping of electron between the PMMA and the IGZO. The voltage drop in the on-state of drive TFT can be analyzed from the ratio of the resistance of load TFT and drive TFT.
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